Design decisions

Each record states a decision about the simulator's structure or timing model, why it was taken, and what follows from it. Records are not edited after the fact; a later decision that changes one says which it replaces.

#	Decision
1	Structural changes are cycle-identical and gated
2	Execute-stage redirects take a configurable latency
3	Every stage but commit sees the hart read-only
4	Frontend latches carry an explicit delay
5	Faults travel with the instruction and are taken at commit
6	Serialization follows the gem5 CPU model each backend stands for
7	A core owns its pipeline
8	The model is crate-private
9	System state is split into harts, cores and an uncore
10	Instruction semantics are separate from timing
11	Accesses take effect where they are served
12	The model follows real cores; gem5 is the reference
13	Stores issue their address and data separately
14	Prefetchers follow the published hardware